TRMS

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TRMS demonstrations

TRMS concept- demonstrates basic concepts in TRMS
A Client to the TRMS environment- a short description of the graphical interface
SUT / Infineon Technologies collaborative application scenario
Encryption- security issues in TRMS
Search a Tool in TRMS

Exemplary application scenarios

Example 1
Presented scenario was described in the paper:
(24-26/06/2005 Szczecin) Verification of trms with IP component design, K. Siekierska, A. Kokoszka, D.Obrębski, N. Ługowski, P. Fraś, T. Kostienko, A. Pawlak, P. Penkala, D. Stachańczyk, M. Szlęzak presented in MIXDES'04 conference

Scenario overview

The design methodology, based on HDL (VHDL or Verilog) and RTL synthesis, is generally the same as in the case of on-site design, but some processes are performed using remote tools. Collaborative IP component design is shown schematically in fig. 1. There are two or three tools respectively to target implementation (standard cell ASIC or FPGA), which should be shared. Synthesis and simulation tools are remotely used in both cases, but the post-synthesis simulation is performed in the case of an ASIC target technology and the post-implementation simulation is performed in the case of an FPGA. The last one has to be preceded by remote implementation and generation of needed files.
Bellow is presented the FPGA workflow, the implementation process (fig. 2). This process consists of five tasks: ngdbuid, map, par, netgen, bitgen (parts of Xilinx ISE). Each of them (excluding the first one) needs as its input the output of the previous one, and there is no need for human interaction, so the automated invocation is very useful in this case.

[Rozmiar: 23263 bajtów] Fig. 1. Schematic of the collaborative IP component design

Implementation part of FPGA design workflow Fig. 2. The part of FPGA design workflow implementated in TRMS

Example 2
Presented scenario was described in the paper:
(19-21/04/2005 Tatranska Lomnica, Slovakia) TRMS Deployment in Distributed Engineering Applications, P. Fras, T. Kostienko, J. Magiera, A. Pawlak, P. Penkala, D. Stachanczyk, M. Szlezak, M. Witczynski, Challenges in Collaborative Engineering Workshop

Scenario overview

Development of complex digital circuits requires a lot of work and close cooperation between engineers responsible for all phases of a design process. To reduce design costs, large design companies often commission small enterprises (SMEs) to develop a selected system component. The collaborative design platform should provide the mechanisms supporting work of all IP designers, and the engineer responsible for integration of the final project.
The established experimental environment supports a design engineer at the stage of system component modelling and verification. At this stage of the design the most important tools are a HDL compiler and simulator, and, of course, a text editor for HDL source code creation. To facilitate collaborative work on the common project, the CVS repository was also used in our experiment.
The first activity within the crated workflow (fig. 3) is an application of the CVS client that is used to checkout design data from the repository located at the Silesian University of Technology in Gliwice, Poland (SUT). Then, apart from the code editor which is invoked locally on the client workstation, the blocks responsible for invocation of the VHDL compiler and simulator installed on a remote site at the Institute of Electron Technology in Warsaw, Poland (ITE) are included. The compilation and simulation reports are sent back and can be viewed in a local text editor. The last activity of the created workflow is again the application of the CVS client that allows storage of project files into the repository.

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Fig. 3. The part of scenario workflow implementated in TRMS